The invention relates to a signal buffer circuit in an integrated circuit for applying an output signal to a connecting terminal of the integrated circuit which also comprises an input signal source, including a series arrangement of a first and a second output transistor connected between the terminals of a supply voltage, a first output electrode of the first output transistor and a first output electrode of the second output transistor being connected to the connecting terminal, and a first driving transistor having a control electrode connected to the input signal source and a first output electrode connected to the control electrode of the first output transistor, a load resistor which is externally connected to the terminal, being connected to either a first voltage whereby the first output transistor conducts while the second output transistor is cut off and whereby the output signal has the same polarity as the input signal, or to a second voltage whereby the second output transistor conducts while the first output transistor is cut off and whereby the polarity of the output signal is opposite to that of the input signal.
Such a circuit is disclosed in Applicants' U.S. Patent Application Ser. No. 944,333, filed Sept. 21, 1978, now U.S. Pat. No. 4,282,447. In this known circuit, the input signal is applied to the base of the driving transistor, which passes signals having the same amplitude and opposite polarities to the output transistors. The output transistors are of the opposite conductivity types, their emitters are interconnected and connected to the connecting terminal. If the load resistor is connected to a positive or to a negative voltage then one of the output transistors conducts, whereby the voltage at the connecting terminal assumes such a value that the other output transistor cannot be conductive.
So a train of pulses having a polarity which can be chosen from outside the integrated circuit is generated with the known circuit. In view of the symmetry of the circuit the driving transistor must, however, be set to approximately half the supply voltages, so that the output voltage is less than this half. In practice, it will be still lower. The circuit is not suitable for uses in which a high amplitude is required, as the output signal at the connecting terminal would have to be amplified while it may have either the one or the other polarity. In addition, if the input signal is not a train of pulses but a direct voltage level, then the two possible output signals are two direct voltage levels between which the difference may be too small to enable a clear distinction.